1. Field of the Invention
The present invention relates to wireless communication systems, such as but not limited to wireless local area networks (WLANs), and in particular, to an 802.11b receiver that contains a packet-based multiplication-free CCK demodulator with a Fast Multipath Interference Cipher (FMIC).
2. Description of the Prior Art
U.S. patent application Publication No. US 2001/0036223 to Webster et al. (“Webster”) discloses a RAKE receiver that is used for indoor multipath WLAN applications on direct spread spectrum signals having relatively short codeword lengths. The RAKE receiver has an embedded decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel inter-codeword interference (also known as Inter-Symbol Interference, ISI) (i.e., bleed-over between CCK codewords).
FIGS. 12–14 of Webster illustrate an Intra-codeword Chip Interference (ICI) canceller which is designed to cancel the ICI generated from the post-cursors through the use of lengthy complex operations (multiplications and additions), including one DFE convolution block and one codeword correlation block for each and every codeword (up to 256 codewords in total), in a 802.11b CCK Decoder. Each of the 64 or 256 ICI outputs is calculated independently from a separate processing path.
In FIG. 12 of Webster, for each and every codeword (256 codewords in total), three basic building blocks are required: (i) one DFE convolution block 1220 which calculates chip-by-chip representation of the ICI before the codeword correlator 1230 using the complex convolution between each codeword (8 complex chips denoted as OW#k CHIP) and up to 8 complex DFE taps, (ii) one chip-by-chip subtractor 1210 which subtracts each of the 8 received complex chips (block 1203) from the outputs of block 1220, and (iii) one codeword correlator 1230 which calculates the correlation between each codeword (8 complex chips) and the results (8 complex chips) from the subtractor 1210. All these operations are complex and are required for each codeword. In short, 256 ICI bias outputs 1212 are calculated independently at blocks 1220, subtracted in parallel at blocks 1210, and then 256 correlations outputs are found from the codeword correlators 1230. Because the input 1223 to each codeword correlator 1230 is now different after the ICI bias correction, this architecture prevents a fast Walsh transform implementation to jointly and effectively calculate the CCK correlations for all CCK codewords.
In another embodiment illustrated in FIG. 13 of Webster, for each and every codeword (64 codewords in total), two basic building blocks (which have the same functions described above) are required: (i) one DFE convolution block 1340 and (ii) one codeword correlator 1330. The number of DFE blocks and correlation blocks required is simplified from 256 to 64. The 64 ICI outputs of blocks 1330 are expanded into 256 ICI outputs from complex operations. Compared to FIG. 12, this architecture calculates the ICI bias for post-CCK codeword correlator correction 1360. Therefore, a codeword correlator to jointly and effectively compute CCK correlations can be effectively implemented using a 64 element fast Walsh transform 1320 and a 1 to 4 expansion 1350. However, each of the 64 post-correlation ICI bias is first calculated using complex convolution 1340 and complex correlation 1330. A 1 to 4 expansion 1330 is then used to generate all 256 post-correlation ICI bias These post-correlation ICI bias are then subtracted from the corresponding 256 correlator outputs of block 1350. To implement this receiver architecture, 64 complex convolution 1340 and complex codeword correlator 1330 need to be performed independently.
In yet another embodiment in FIG. 14 of Webster, for each and every codeword (256 codewords in total), two basic building blocks (which have the same functions described above) are also required: (i) one DFE convolution block 1440 and (ii) one complex codeword correlator 1430. Webster states the fact that the DFE taps can be pre-calculated and pre-stored. Again, the 256 ICI outputs are calculated independently at blocks 1440, and then 256 correlations are found at the outputs of block 1430.
In summary, Webster's architecture requires significant hardware complexity and the execution of large numbers of complex operations (complex multiplications and additions that are required for complex convolution and complex correlation). As a result, large power consumption, complex hardware, and long processing times will be required to implement the embodiments described in FIGS. 12–14 of Webster.